To form a via hole in a semiconductor device, a conventional process forms an insulating layer over a metal layer. Next, a via hole is made by dry-etching the insulating layer with plasma. A TiN layer is deposited over the metal layer and used as an etch-stop layer. To remove etching-residues such as polymers on the TiN layer and residuals from the insulating layer, a predetermined portion of the TiN layer is over-etched. This also reduces electrical resistance between a metallic material to be filled into the via hole and a thin TiN layer. Next, the thin TiN layer is deposited on the inside of the via hole. Next, the metal is filled into the via hole.
FIGS. 1a through 1c are cross-sectional views illustrating a prior art process for forming a via hole in a semiconductor device. Referring to FIG. 1a, a photoresist pattern 2 for making a necessary via hole is formed on an insulating layer 1 through a photoresist development process.
Referring to FIG. 1b, a via hole 3 is formed by dry-etching the insulating layer 1 with plasma. The diameter of the upper part of the via hole 3 is larger than that of the lower part of the via hole 3. The diameter of the lower part of the via hole 3 is smaller than that of the required via hole 3.
Referring to FIG. 1c, a thin metal layer 6 is deposited on the inside of the via hole 3. Next, the via hole 3 is filled with a metallic material 7. The process for forming the via hole 3 is thus completed.
FIG. 1d is a cross-sectional view of a prior art via hole as seen through a SEM (Scanning Electron Microscope). As shown in FIG. 1d, the diameter 8 of the lower part of the via hole 3 is smaller than the diameter 9 of the upper part of the via hole 3.
Typically, prior art methods make a via hole by dry-etching an insulating layer with plasma. More specifically, the via hole for connecting metal layers is typically formed by etching the insulating layer deposited on a metal layer. However, the diameter 9 of the lower part of the via hole 3 is different from the diameter 8 of the upper part of the via hole 3 due to etching-residues such as polymers generated in the conventional etching process. As the diameter 9 of the lower part of the via hole 3 (which is in a direct contact with the bottom metal layer) is decreased, the contacting area 5 with the metal layer becomes relatively small. Thus, semiconductor devices with via holes fabricated using conventional methods suffer from problems such as current loss when power is applied.
Tran et al., U.S. Pat. No. 6,232,221, describes a method for forming borderless via holes by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer.
Tabara, U.S. Pat. No. 6,137,175, describes a method for fabricating a semiconductor device with multi-layer wiring.
Tran et al., U.S. Pat. No. 6,133,142, describes a method for fabricating reliable via holes by providing an adequate landing area without increasing the size of the underlying feature.